Two-step chemical mechanical polish surface planarization technique

摘要

A method of planarizing a dielectric coating applied over an underlying structure on an integrated circuit wafer employs a two-step chemical mechanical polishing (CMP) process. The underlying structure is characterized as having elevated areas and recessed areas. The wafer is first prepared by applying a first polish stop on the elevated areas, then depositing a layer of dielectric (oxide) over at least the recessed areas, and finally depositing a second polish stop material polysilicon over the resulting dielectric coating. The first step in the two-step CMP is polishing the second polish stop using a slurry that attacks the second polish stop until the second polish stop is substantially removed over the elevated areas. The second step is polishing the dielectric coating that remains using a second slurry that attacks the dielectric at a faster rate than it attacks either the second or first polish stop until the first polish stop is exposed. In this process, the second polish stop protects the recessed areas. An extension of this method does not require a first polish stop nor does it polish through to the underlying structure. Instead, this alternative method leaves a reduced dielectric layer covering the underlying structure which is planar. <IMAGE>