| 摘要 |
A multiport memory having a serial input port receives serial data into a pipeline. The pipeline is emptied in response to a transfer signal at a time before the parallel transfer of data from a serial to parallel conversion register into memory. The pipeline in one embodiment includes in serial connection an input latch, a first isolation gate, a write register, a second isolation gate, an I/O bus, and means for equilibrating the I/O bus. The pipeline is controlled by write control logic so that the pipeline is emptied while equilibration of digit lines is being disabled. In a video random access memory (VRAM) embodiment, a tap counter and hold register specify the next position for serial access to the serial access register. These elements are controlled by write control logic in response to a transfer signal and a serial clock signal to allow the tap counter to increment while emptying the pipeline. When the pipeline is already empty, no increment takes place. In another embodiment, the input data latch is clocked toward the end of the serial clock cycle rather than near the beginning. The resulting negative setup time is useful in system designs wherein the serial clock is applied directly to processor logic to produce serial data and to multiport memory to receive the serial data after it has been produced.
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