| 摘要 |
The inputs of matching detection circuits 4i (i=0 to 3) is connected with each of one-bit data lines to one of a plurality of memory blocks 10 to 13, with its output connected to data terminal 2i. The input of distribution circuit 3i are connected to the data terminal 2i and its plurality of outputs, which are insulated from one another and output data corresponding to the data provided to the inputs are connected to the data lines that are connected to the inputs of the matching detection circuit 4i. A control circuit 16 that, during a data write in data compression test mode, invalidates the output from the matching detection circuit 4i to the data terminal 2i and validates outputs from the distribution circuit 3i to the data lines, and during a data read in the the data compression test mode, validates the output from the matching detection circuits 4i to the data terminal 2i and invalidates the outputs from the distribution circuits 3i to the data lines.
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