发明名称 |
Dynamic clock mode switch |
摘要 |
A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.
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申请公布号 |
US5579353(A) |
申请公布日期 |
1996.11.26 |
申请号 |
US19950499066 |
申请日期 |
1995.07.26 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
PARMENTER, KEVIN C.;TAKAHASHI, YUTAKA |
分类号 |
G06F1/08;H03L7/06;H03L7/095;H03L7/183;H04L7/00;H04L7/033;(IPC1-7):H03D3/24 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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