Pipelined arrangement including data processing storages having dynamic latches for reducing delay in data processing

摘要

A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangement is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.