| 摘要 |
A frame buffer memory of the present invention has a serial access memory portion including m normal units, a redundancy unit, and a serial selector. Each of the normal units includes four sense amplifiers, one data register provided corresponding to these sense amplifiers, and four transfer gates provided corresponding to these sense amplifiers and each connected between a corresponding sense amplifier and the data register. The redundancy unit includes two redundancy sense amplifiers, one redundancy data register provided corresponding to these redundancy sense amplifiers, and four redundancy transfer gates provided corresponding to these sense amplifiers. Two of the redundancy transfer gates are connected between a corresponding redundancy sense amplifier and the redundancy data register. m transfer gates are provided corresponding to m data registers, and a redundancy transfer gate is provided corresponding to the redundancy data register. The m transfer gates in the m normal units are all turned on in response to a corresponding one of four control signals. Two transfer gates in the redundancy unit are both turned on in response to corresponding two of the four control signals.
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