发明名称 METHOD AND SYSTEM FOR FETCH CONTROL OF INSTRUCTION AND DATA
摘要 PROBLEM TO BE SOLVED: To fetch an instruction and data beyond many underived branches by encoding speculation at the time of compile related with a conditional branch which is present between a point of time when a prefetch request is started and a point of time when prefetched data are necessary, and specifying it to hardware at the time of execution. SOLUTION: A memory unit 102 stores instructions or data in an instruction cache 104 and a data cache 106, and divides each into blocks. Each block is fetched to a decode unit 110 by an instruction fetch unit 108. On the other hand, the fetch of the data block from a data cache 106 to a functioning units 116-1-116-K is processed by a data fetch unit 118. Then, speculation is encoded at the time of the compile of a conditional branch which is present between a point of time when a prefetch request for the speculation tag of an entry 200 is started, and a point of time when the prefetched data of a control unit 124 are necessary, and specified to a completing unit 122 at the time of execution.
申请公布号 JPH08305565(A) 申请公布日期 1996.11.22
申请号 JP19960081784 申请日期 1996.04.03
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 PURADEIIPU DABII
分类号 G06F9/38;G06F12/12;(IPC1-7):G06F9/38 主分类号 G06F9/38
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