| 摘要 |
PURPOSE: To reduce the hardware amount and to attain a high operation speed by reducing the number of inputs to an adder tree in the product sum arithmetic unit. CONSTITUTION: A bit width extender 1 applies 0 extension to 1-bit to a multiplicand X in the case of arithmetic operation without a code and applies sign extension of 1-bit in the case of arithmetic operation with a code. A 0 extender Z applies 0 extension by 2bits to a multiplier Y. A decoder 4 of a booth segments an output of a 0 extender 2 in the unit of 3bits while shifting a segmentation start position from the most significant bit by 2-bit each toward low-order bits and generates 1st to (k-1)th partial products and k-th particle product based on the segmented value and an output of the bit width extender 1. A selector 5 selects the k-th partial product in the case of arithmetic operation without code or selects an output of the code extender 3 (sum Z subjected to code extension) in the case of arithmetic operation with code. A k-input adder tree 6 adds the 1st to (k-1)th partial products and an output of the selector 5. |
