| 摘要 |
PURPOSE: To easily generate test data on the basis of real data by sending/ receiving data between a data processing unit and a target device and storing sequentially test basis data to a memory depending on a bus cycle pulse. CONSTITUTION: Plural timing counter circuits 61 are respectively provided to each signal line on a data transfer bus 11 and count a timing clock and generating data at a leading and trailing timing of each signal as a count. The count is returned to a head address of a memory 8a and a count from an address generation circuit 7 is returned to a memory 8b and they are stored in the memories 8a, 8b alternately as synthesized test basis data. Then, data are sent/ received between a data processing unit of a host computer 20 and a target device 12 and the basis data are stored sequentially in the memories 8a, 8b depending on a bus cycle pulse. Thus, timing data can be easily generated. |
