TWO-DIMENSIONAL ORTHOGONAL TRANSFORMATION ARITHMETIC UNIT

摘要

PURPOSE: To decrease a circuit scale of the orthogonal transformation device such as a discrete cosine transformation device. CONSTITUTION: A two-port memory is used as a transposition memory 7 where output data from a linear DCT arithmetic circuit 6 are transposed and a transposition memory control circuit 10 reads written data out one - (2N-2) clocks before the writing of one block is completed and then writes following blocks in parallel to their read successively to the writing. The respective blocks are written while the row order and column order are inverted alternately for every block, and the respective blocks are read out in order different from the writing order of the blocks. For the operation, a circuit 12 which generates the read address 22 of the transposition memory 7 generates the read address by alternating two kinds of method for a case wherein the address increase, one by one, and a case wherein the address increase by N at each time at every (N×N)th time and generates the write address by delaying the read address by a time of one of 1 to 2N-2 clocks through a delay circuit 13.