| 摘要 |
PURPOSE: To suppress stripping of SOG film and generation of crack with thermal stress by forming an interlayer insulation layer, comprising the SOG film having a plurality of dummy via holes and an insulation film deposited by CVD, on a preliminary region. CONSTITUTION: In the outer circumferential region of a chip, a via holes is made through an electrode pattern 4a for bonding pad and dummy via holes are opened in an electrode pattern 4c metal ring seal and dummy electrode patterns 4b1-4b3. A second interconnection layer 7 is then formed on the entire surface of substrate. Subsequently, the substrate is coated, on the entire surface, with resist and passed through exposure and develop steps thus forming a resist pattern. Finally, a passivation film 8 is etched using the resist pattern as an etching mask thus exposing the electrode of bonding pad and the scribe region. |
