Fault tolerant memory system

摘要

A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.