VERY LOW NOISE, WIDE FREQUENCY RANGE PHASE LOCK LOOP
摘要
A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.
申请公布号
WO9637044(A1)
申请公布日期
1996.11.21
申请号
WO1996US07098
申请日期
1996.05.16
申请人
VLSI TECHNOLOGY, INC.;BHUSHAN, BHARAT;ARCUS, CHRISTOPHER, A.;TA, PAUL, D.
发明人
BHUSHAN, BHARAT;ARCUS, CHRISTOPHER, A.;TA, PAUL, D.