| 摘要 |
<p>A monitor CPU (20) includes inputs for sensors (13) to measure selected environmental conditions and a connection to a semiconductor device that can temporarily disable the device in case an unacceptable environmental condition is detected. This is particularly useful where the semiconductor device is in a field programmable gate array (FPGA). The monitor CPU can be loaded with a unique identification number to allow communication over a bus and in turn use that as a means for a host to selectively access the connected semiconductor device. The monitor CPU (20) can be connected to DRAM (40) which ordinarily also is connected to and controlled by a semiconductor device, such as an FPGA (30). During certain periods when the device (FPGA) (30) is unavailable the monitor CPU (20) can initiate a DRAM (40) refresh circle as needed. The monitor CPU (20) can be connected directly to the program pin(s) of an (FPGA) (30) for controlling the configuration state of the FPGAS (30).</p> |
