发明名称 Serial access memory with reduced loop-line delay
摘要 <p>According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an enabling signal that enables access to a certain number of bits at a time. By operating together, the shift registers enable simultaneous access to a multiple of that number of bits. This multiple can be varied to design serial access memories with different word widths. According to another aspect of the invention, there need be only one shift register, but its stages are interleaved. The enabling signal is shifted from a first end of the shift register to a second end, skipping every other stage, then shifted back from the second end to the first end through the stages that were skipped. This operation is repeated cyclically. &lt;IMAGE&gt;</p>
申请公布号 EP0743649(A2) 申请公布日期 1996.11.20
申请号 EP19960106763 申请日期 1996.04.29
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 IWAKIRI, ITSURO
分类号 G11C11/41;G11C7/10;G11C8/04;G11C11/401;(IPC1-7):G11C7/00 主分类号 G11C11/41
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