| 摘要 |
PURPOSE:To shorten the cycle time when no conflict is produced between the read data and the write data by changing the cycles of both reading and writing actions after the reading action. CONSTITUTION:A memory 300 sends an acception signal 35 back to a request device 100 from a priority circuit 15 and transfers a reading action identification signal 36 to the request devices 100 and 200 from a main control circuit 16 before the timing of the next request signal in accordance with the priorities of request signals 33 and 34 received from the request control circuits 1 and 2 of the devices 100 and 200 like an arithmetic processor and an input/output processor, etc. The circuits 1 and 2 receive the signal 36 to secure the AND with the write instruction identification signals 23 and 24 of the next requests and control the next requests to change the cycles of both reading and writing action after the reading action. In such a way, the cycle time can be shortened when no conflict is produced between the read and write data. |
