发明名称 Arithmetic circuit for adaptive equalizer of LMS algorithm of reduced amount of operation
摘要 An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm. Includes a real operation part computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step coefficient, and computing a second product between an imaginary part signal of the data sequence and a product of an imaginary part signal of the error sequence and a step coefficient. Either of the first and second products is negative. The real operation part further computes a real part of an adaptation coefficient from the first and second products. An imaginary operation part computes a third product between the imaginary part signal of the data sequence and a product of the real part signal of the error sequence and the step coefficient, and computes a fourth product between the real part signal of the data sequence and a product of the imaginary part signal of the error sequence and the step coefficient, so as to obtain an imaginary part of an adaptation coefficient from the third and fourth products.
申请公布号 US5576983(A) 申请公布日期 1996.11.19
申请号 US19940361283 申请日期 1994.12.22
申请人 NEC CORPORATION 发明人 SHIOKAWA, TOSHIMICHI
分类号 H03H17/02;G06F17/00;H03H21/00;H04L25/03;(IPC1-7):G06F7/52 主分类号 H03H17/02
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