Method for manufacturing an EPROM

摘要

A memory cell manufacturing method includes the steps of: providing a silicon substrate with buried regions that are spaced by a channel; depositing a gate oxide layer over the substrate; removing a portion of the gate oxide layer which is over the channel; depositing a first polysilicon layer over remaining portions of the gate oxide layer and over exposed portion of the substrate; growing an insulating layer over the polysilicon layer; providing a first mask on the insulating layer, the mask having a length shorter than that of the insulating layer and two end portions which overlap respectively the buried regions; etching portions of the insulating layer and the polysilicon layer not covered by the mask; depositing a thin oxide layer over a remaining portion of the insulating layer; depositing a second polysilicon layer over the thin oxide layer and over the buried layers; providing a second mask, which has a width narrower than that of the second polysilicon layer, on the second polysilicon layer to define a control gate region; etching portions of the second polysilicon layer not covered by the second mask so as to form a control gate; growing a thick oxide layer on a remaining portion of the second polysilicon layer; and etching the insulating layer and the first polysilicon layer with the thick oxide layer serving as a mask.