Load voltage applying circuit for non-volatile semiconductor memory

摘要

The voltage applying circuit includes two control units for respective memory block selection and wordline selection. The non-volatile memory is provided with several memory blocks, each having row and column array-formed memory cells and each cell being connected to several series connected memory FETs. Also included are an address buffer, a predecoder, and a voltage generator for supplying e.g. load, read, write, erase, and program voltages to detect defects inside a memory block. The memory block selection control unit selects the block to which a program voltage should be applied, as well as the following block to be chosen. The wordline selection control unit selects the wordline to which the load voltage should be applied. In a defective cell detection mode, the load voltage is applied to a wordline of a chosen memory block and an earth voltage is supplied to a wordline of a non-chosen block, the chosen wordline being connected to a memory transistor in the selected block. This test is repeated for each block.