| 摘要 |
The present invention relates to a cache Static Random Access Memory, and includes an SRAM cell array unit having a 4 wayx64 set cell array structure; a write circuit unit for renewing one bit line of 4 wayx64 set SRAM cell array after receiving a read way selection signal(tRway) applied from a cache controller, and an address applied from a memory management unit, a pre-charge unit for charging a bit line of SRAM cell array unit to a logic high state; a word line decoder unit for selecting one row of 64 rows of an SRAM cell array unit; a sense amplifier unit for amplifying a weak signal which is, via a bit line, read from a cell of a row selected by the word line decoder unit; a comparator unit for outputting a signal(Taghit#0) by comparing an address applied from the write circuit unit with an output of the sense amplifier unit; and a test circuit for calculating and then outputting a node(AA) value, which is used for determine as to whether or not an SRAM cell is normal according to two signals Dphi1b and Phi2 after receiving data read from the SRAM cell array via the sense amplifier unit and a read way selection signal(tRway) applied from a cache controller. |
