发明名称 FRAME PERIOD MONITORING SYSTEM
摘要 PROBLEM TO BE SOLVED: To obtain the maximum balance between hardware and software so that cost, necessary space and design complication can be minimized, and frame tracking resolution can be maximized. SOLUTION: This system is constituted so that when the reception of an incoming frame is communicated by a source port, a timer 164 can be realized related with a frame. Also, this system includes a processor 100a constituted so that a successive timer state 144 can be outputted, and a deleting means connected with the processor for receiving the timer state which judges the lapse of a prescribed deleting period based on the timer state. This system includes a logical network 100b for allowing the deleting means to generate a deletion signal 147 after the lapse of the prescribed deleting period, and the processor is used as a timing incrementer, and logical judgment is assigned to the high speed logical network by the processor.
申请公布号 JPH08298536(A) 申请公布日期 1996.11.12
申请号 JP19960012077 申请日期 1996.01.26
申请人 HEWLETT PACKARD CO <HP> 发明人 ROBAATO EICHI GURANTO;DEIBUITSUDO BUTSUKU;GUREGORII TEII SARIBUAN
分类号 H04B10/08;H04B10/02;H04L12/26;H04L12/56;H04L29/14 主分类号 H04B10/08
代理机构 代理人
主权项
地址