发明名称 VIDEO SIGNAL PROCESSOR
摘要 <p>PURPOSE: To constitute a circuit in a complete IC by adopting a signal whose line is not locked as a clock. CONSTITUTION: An ADC 141 converts an input composite video signal into a digital signal based upon a fixed frequency clock outputted from an oscillator 140 and a base band chrominance signal is obtained from the digital signal through a BPF 144 and color demodulation circuit 145. The phases of the video signal from the ADC 141 and the base band chrominance signal from the circuit 145 are respectively shifted by phase shifting circuits 1420 to 1422. On the other hand, a clock timing reproducing synchronizing signal is generated from a synchronization detecting circuit 1424, an error between the synchronizing position of the synchronizing signal and that of the video signal from the circuit 1420 is found out and the phases of the video signals are shifted by respective circuits 1420 to 1422 based upon the error to allow the synchronizing positions to approximately coincide with prescribed phase relation. Video signals outputted from the circuits 1420 to 1422 are decoded by respective video processing part 143, 149, 1419 to obtain R, G and B signals.</p>
申请公布号 JPH08298674(A) 申请公布日期 1996.11.12
申请号 JP19950336740 申请日期 1995.12.25
申请人 TOSHIBA CORP 发明人 YAMADA MASAHIRO
分类号 H04N11/04;H04N9/44;H04N11/14;(IPC1-7):H04N11/04 主分类号 H04N11/04
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