发明名称 INTERRUPTION CIRCUIT OPERABLE AT A HIGH SPEED
摘要 In an interruption circuit, each of a multiplicity of interruption generating units (12) is for generating an interruption signal upon occurrence of an interruption request. A scanning arrangement scans the units to specify one of them at a time as a particular unit and to supply the signal generated by the particular unit to a CPU (11) as a particular signal. A response supply arrangement supplies the particular unit with a response produced by the CPU upon receipt of the particular signal. Supplied with the response, the particular unit supplies the CPU with an interruption vector which is specific to each unit and makes the CPU interrupt its operation related to the particular unit. Preferably, the scanning arrangement comprises a scanning circuit (16) and a first plurality of polling circuits (17), each for a second plurality of generating units with a response control circuit (27) made to correspond thereto.
申请公布号 CA2066011(C) 申请公布日期 1996.11.12
申请号 CA19922066011 申请日期 1992.04.14
申请人 NEC CORPORATION 发明人 MURAI, MASAO
分类号 G06F9/48;G06F13/24;(IPC1-7):G06F9/46 主分类号 G06F9/48
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