发明名称 Fail-safe MOS shutdown circuitry
摘要 A dual discharge network is shown discharging any residual charge on the gates of MOSFET's used to protect a device from over voltages. The dual discharge networks are separately responsive to a positive or negative voltage at an input terminal such as an I/O input terminal, for example. Bias to each of the discharge networks is provided by the positive or negative I/O voltage and power to the transistors within each discharge network is provided by the MOSFET gate charges. In this way, a conduction path is formed between the positively and negatively charged MOSFET gates driving the gates towards ground, driving the MOSFETs to non-conduction and isolating a protected device from a I/O over-voltage where positive or negative.
申请公布号 US5574609(A) 申请公布日期 1996.11.12
申请号 US19940180267 申请日期 1994.01.12
申请人 HARRIS CORPORATION 发明人 LEIDICH, ARTHUR J.
分类号 H03K17/0814;H03K17/082;(IPC1-7):H02H9/00 主分类号 H03K17/0814
代理机构 代理人
主权项
地址