| 摘要 |
PURPOSE: To considerably decrease an area for arranging a global bus and a control signal line without considerably decelerating speed for transmitting data. CONSTITUTION: A lot of processor elements A, B, C and D constituting the array processor are respectively connected by local buses 15 and 16 one and another and lateral direction and longitudinal direction global buses 25 and 26 are provided at intervals of a prescribed number of the respective processor elements A, B, C and D. When locally transmitting data processed by the respective processor elements, the local buses 15 and 16 are used and when transferring data stored by the local data transmission to a distant processor element, the longitudinal and lateral global buses 26 and 25 are used. Thus, the area for arranging the global buses 25 and 26 and the control signal line can be considerably reduced almost without decelerating the speed of data transmission. |
