| 摘要 |
PURPOSE: To reduce the total wiring area of a control signal line for controlling respective processor elements constituting the array processor. CONSTITUTION: 1st-4th registers 1a-1d provided at plural adjacent processor elements 10a-10d respectively each are connected together in common like the 1st registers 1a are connected each other and like the 2nd registers 1b are connected each other, computing elements inside the processor elements are successively connected through read buses 3a-3d and write buses 4a-4d to the registers like a computing element 2a inside the 1st processor element 10a is connected to the 1st register 1a or a computing element 2b inside the 2nd processor element 10b is connected to the 2nd register 2b, and the registers 1a-1d each provided inside the respective processor elements 10a-10d can be commonly controlled. Thus, it is enough to wire a control signal line 5 to any one of respective processor elements 10a-10d so that the total wiring area of the control signal line 5 can be reduced. |
