Error detection circuit for power up initialization of a memory array

摘要

A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and slave portions, apparatus for placing data from the first memory cell into the master portion of the shift register and shifting the data into the slave portion of the shift register, apparatus for placing the data from the first memory cell into the second memory cell, apparatus for placing the data in the second memory cell back into the master portion of the shift register, and logic circuitry for testing the condition of the data in the master portion of the shift register against the condition of the data in the slave portion of the shift register to determine if the data has been correctly written into the second memory cell.