Emulation system having a scalable multi-level multi-stage programmable interconnect network

摘要

A scalable multi-level multi-stage network topology is employed to interconnect reconfigurable logic elements within the FPGA, inter-FPGA, interlogic boards, and inter-backplanes. More specifically, under the presently preferred embodiemnt, an on-chip 3-stage inter-logic element crossbar network is provided to each FPGA for interconnecting the reconfigurable logic elements and the I/O pins of the FPGA. A two level two-stage inter-FPGA crossbard network is provided to interconnect the FPGAs and I/O pins of the logic board. A two-level two-stage inter-board crossbar network is provided to interconnect the logic boards or I/O boards for interconnecting the logic elements to external devices. Finally, a single-stage inter-backplane network and a number of PCBs are provided to interconnect multi-backplanes to form a multi-crate system.