| 摘要 |
FIELD: computer engineering; computer-aided control systems affording synchronous real-time operation of several machines of multicomputer systems. SUBSTANCE: device is provided with second delay element, second AND gate, and D flip-flop; output of first OR gate is connected to R input of D flip-flop and to input of second pulse delay element whose output is connected to clock input of D flip-flop and to first input of second AND gate whose output is connected to second input of second OR gate; D flip-flop output is connected to second inputs of AND gate. EFFECT: simplified design of device due to improved analysis of sync pulse master oscillator failure. |
