| 摘要 |
FIELD: automatic control and computer engineering. SUBSTANCE: device has image source, video amplifier, video signal selector, synchronizing and control unit, first counter, second counter, X-rate boundary separating unit, Y-rate boundary separating unit, AND gate unit, video monitoring unit, data receiving and transmitting unit, level selecting unit incorporating first and second amplitude discriminators, pulse generator, computer, unit combining old and new information and searching for intersection points, third counter, packed-area main storage unit, control-vector main storage unit, intersection-point main storage unit, control-vector generating unit, first and second shift-register units, first one having first and second shift registers RGa, RG2 and second unit, third and fourth shift registers RG3, RG4; control-vector generating unit has buffer address register unit, addition circuit, address increment read-only memory, point repetition eliminating circuit, address demultiplexor, point-to-path assignment analyzing unit, current area read-only memory, circuit for comparison with end point of path, current mode-of-operation storage circuit, circuit for building arc between two points on path; unit combining old and new information and searching for intersection points has first encoder, parallel-codes comparison circuit, first and second data storage registers, OR gate unit, third data storage register, AND gate unit, second encoder; buffer address register unit has first, second, third, and fourth storage registers, first and second logic units; address increment read-only memory has read-only memory unit, first address counter, third logic unit; address bus demultiplexor has demultiplexor, first NOR gate, fourth logic unit; point-to-path assignment analyzing unit has multiplexor, point counter, first binary code comparison circuit, second and third AND gates, fifth logic unit; current mode-of-operation storage circuit has fifth storage register with first logic circuit at inputs, sixth logic unit; circuit for comparison with end point of path has end point storage register, second parallel-code comparison circuit, second and third OR gates; circuit for building arc between two points of path has subtracter, third encoder, second logic circuit at inputs of the latter, second address point counter, seventh logic unit. EFFECT: enlarged functional capabilities, improved speed of data transmission and input in computer. |
