PERIPHERAL CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

摘要

Integrated circuitry includes, a) a first array of electronic devices (32) comprising a series of conductive runners (33) extending outwardly of the memory array with adjacent runners having a device pitch of 0.6 micron or less in a pitch direction, b) a second array of electronic devices (43) peripheral to the first array, the 0.6 pitch conductive runners of the first array extending into the second array, at least some of the conductive runners of the series having respective disjointed gaps (82) therewithin within the second array, the gaps being aligned with one another in the second array, c) a cross running conductor (90-97) extending substantially parallel with the pitch direction and over the aligned gaps within the second array, d) an insulating dielectric layer provided relative to the disjointed gaps within the second array; and e) a series of electrically conductive plugs (105-112) provided within the insulating dielectric layer and running substantially perpendicular to the pitch direction within the second array, the conductive plugs respectively extending across the respective gaps between and electrically interconnecting the respective disjointed conductive runners within the second array, the cross running conductor extending elevationally over the conductive plugs. Memory integrated circuitry is also disclosed which incorporates electrically conductive plugs (47, 50, 52) which electrically interconnect disjointed active area regions (431, 421, 411, 401, 391) of different transistors in pitch cells.