发明名称 Verfahren zur Herstellung einer Leiterplatte und durch besagtes Verfahren hergestellte Leiterplatte selbst
摘要 Disclosed is a method of manufacturing a circuit board comprising an insulating substrate (1) and a conductor pattern (7) of a low resistivity which can be prevented from being peeled off the substrate by a thermal stress. The method comprises the step of forming an insulating layer on an insulating substrate (1), the insulating layer being provided with a groove having a depth of at least 20 mu m and shaped like a conductor pattern which is to be formed later, the step of filling the groove of the insulating layer with a paste composition consisting of a powdery material capable of forming an electrically conductive metal, a fine particles having a thermal expansion coefficient smaller than that of the electrically conductive metal, the fine particles being used in an amount of 0.5 to 20% by volume based on the amount of the electrically conductive metal, and an organic binder, and the step of baking the paste composition so as to form a conductor pattern (7) on the insulating substrate (1), the conductor pattern (7) containing as a main component the electrically conductive metal and the fine particles having a thermal expansion coefficient smaller than that of the metal, the fine particles being dispersed in the electrically conductive metal in an amount of 0.5 to 20% by volume based on the amount of the electrically conductive metal. <IMAGE>
申请公布号 DE69117819(T2) 申请公布日期 1996.11.07
申请号 DE1991617819T 申请日期 1991.06.27
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 UENO, FUMIO, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP;KASORI, MITSUO, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP;GOTO, YOSHIKO, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP;HORIGUCHI, AKIHIRO, C/O INTELLECTUAL PROPERTY DIV., MINATO-KU, TOKYO 105, JP
分类号 C23C16/18;C23C30/00;H05K1/03;H05K1/09;H05K3/00;H05K3/10;H05K3/12 主分类号 C23C16/18
代理机构 代理人
主权项
地址