<p>The polishing pad (23, 36, 50) includes a polishing layer (52) and a rigid layer (54). The rigid layer (54) adjacent the polishing layer (52) imparts a controlled rigidity to the polishing layer (52). The resilient layer (56) adjacent the rigid layer (54) provides substantially uniform pressure to the rigid layer (54). During operation, the rigid layer (54) and the resilient layer (56) apply an elastic flexure pressure to the polishing layer (52) to induce a controlled flex in the polishing layer (52) to conform to the global topography of the wafer surface while maintaining a controlled rigidity over the local topography of the wafer surface. <IMAGE></p>
申请公布号
DE69122441(D1)
申请公布日期
1996.11.07
申请号
DE1991622441
申请日期
1991.06.15
申请人
NATIONAL SEMICONDUCTOR CORP., SANTA CLARA, CALIF., US
发明人
PIERCE, JOHN MORLEY, PALO ALTO, CA 94303, US;RENTELN, PETER HENRY, CUPERTINO, CA 95014, US