INSTRUCTION MEMORY LIMIT CHECK IN MICROPROCESSOR

摘要

A method and apparatus for efficiently detecting and reporting instruction segment limit violations in the prefetch stage of a pipelined processor and reporting an exception only when it is no longer possible to branch around the limit violation. Whenever a branch occurs in a processor, the execute stage of the processor calculates the number of bytes between the branch destination address and the last valid instruction byte which can be sequentially addressed from the branch destination address. The value is provided to a register in the prefetch stage of the processor. In the prefetch stage, unless and until another branch occurs, the value is decremented each cycle by the number of bytes prefetched during that cycle. If a branch is executed, the new branch destination address is provided to the register from the execute stage. When the value reaches zero, prefetching is halted, but the rest of the pipeline is allowed to continue normal operation until there is no longer a possibility that a branch instruction exists in the pipeline between the prefetch stage and the execute stage. Only then is a segment limit exception reported to the execute stage upon the next program counter pulse.