SCHALTUNGSANORDNUNG ZUR REDUZIERUNG DER KAPAZITAET EINES LEISTUNGSSCHALTERS

摘要

A circuit arrangement is provided to mitigate the parasitic capacitance that typically is associated with solid state switches which are designed to carry high current magnitudes. By disposing a capacitive component in series with a power switch which, in turn, is connected in series with an inductive component, the overall capacitance of the switch and capacitive component are significantly reduced. In a preferred embodiment of the present invention, the capacitive component is a diode with a voltage potential provided at the cathode of the diode so that the parasitic capacitance of the diode can be varied to tune the total circuit for the purpose of achieving a specific resonant frequency. In applications where high frequency signals are injected into the circuit for purposes of measuring a parameter, such as rotor position, the present invention is beneficial because of the ability to tune the frequency resulting from the residence of the series LC circuit which comprises a conductive component, such as a motor stator winding, and a capacitive component, such as a power switch which possesses an inherent parasitic capacitance. Another benefit of the present invention is the fact that it makes possible the use of smaller components in a snubber network associated with the inductive component because of the increase in resonant frequency achieved by the decrease in capacitance of the series LC circuit.