Decoding circuit for addressing word lines on integrated circuit e.g. IC memory

摘要

The decoding circuit is used to address N, e.g. four, word lines (WL1-WL4) in an integrated circuit. A first partial decoder (1) addressed by first addressing signals (XA,XB,XC) with signal levels at ground and VCC, has a first level converter (2), whose output (WLT) is at ground and at a further third potential level less than both ground and VCC. The output is submitted to each of the word lines via CMOS inverters (I1). Every line has a second partial decoder (3) which generates a load/un-load signal per line, and is addressed by second addressing signals (XD1-XD4) with a level between ground and VCC, and each of which has a second level converter (4), from each output (OUT1-OUT4) of which a load signal (WD1-WD4) emerges at ground and the third potential and into the inverter. A further first partial decoder with different selectable address lines enables a choice of a further four word lines (WL5-WL8).