发明名称 Method and circuit arrangement for processing variable symbol rates
摘要 The invention is related to a method and circuit arrangement for processing a received signal in a variable symbol rate system, such as a digital television system. In the method and arrangement according to the system, a received signal is sampled at a fixed sampling frequency (ff) that is higher than the symbol frequency of any one of the received signals. The resulting sample sequence is converted to another sample sequence the sampling frequency of which equals the symbol frequency (fi) of the received signal or its integer multiple. Then the samples are filtered (8) and signal value decisions are made (9) for the filtered samples. Conversion of the sampling frequency is advantageously performed using a so-called modified Farrow-type fractional delay filter (6) which is controlled using a control signal proportional to the delay of each sample. Using the method and arrangement according to the invention it is possible to process received signals the symbol frequencies of which are arbitrary within set limits. <IMAGE>
申请公布号 EP0741472(A2) 申请公布日期 1996.11.06
申请号 EP19960106338 申请日期 1996.04.23
申请人 NOKIA TECHNOLOGY GMBH 发明人 VAELIMAEKI, VESA;LAAKSO, TIMO;HENRIKSSON, JUKKA
分类号 H03H17/06;H04L7/00;H04L7/02;H04L7/027;H04L27/00;H04L27/227;H04N7/24;(IPC1-7):H04L7/02 主分类号 H03H17/06
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