Method and apparatus for a phase-locked loop circuit with holdover mode

摘要

A phase-looked loop circuit with holdover mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-looked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.