Digital phase-looked loop circuit

摘要

Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error DELTA N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error DELTA N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.