Pipeline signal processor

摘要

This invention discloses an improved signal processor comprising first to third arithmetic units forming a pipeline structure, first to third control information hold circuits each of which holds control information for its corresponding arithmetic unit, first to third selection circuits, and first to third signal transfer circuits. Transfer of a selection signal is delayed by a proportional interval of time to the processing time of each arithmetic unit. In order to perform the switching of arithmetical operations in each arithmetic unit according to the data flow in the pipeline processing, each selection circuit selects among the control information hold circuits depending on the selection signal transferred and provides control information held in a selected control information hold circuit to a corresponding arithmetic unit.