发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY
摘要 PURPOSE: To decrease kinds of FETs in a circuit constitution having writing power source voltage exceeding breakdown strength by constituting a writing load with conductive FETs being complementary to FET outputting cell writing voltage. CONSTITUTION: Writing circuits 125, 126,... control connection of writing loads 104,... for bit lines 111, 112,... specified by output 115, 116,... of a column decoder 117 in accordance with a signal of a writing data line 114. A bias circuit 118 outputs bias voltage of 8V to a bias voltage line 103 by step-down of writing power source voltage 101 of 10V, and sets cell writing voltage to 6V. A N type transistor 102 receives a signal of the bias voltage line 103 in a gate electrode, and outputs cell writing voltage to a cell writing voltage line 105 connected to a source electrode. The writing load 104 is constituted with P type transistors being complementary to the N type transistor 102. Any voltage between electrodes of the N type transistor 102 does not exceed 6V.
申请公布号 JPH08293197(A) 申请公布日期 1996.11.05
申请号 JP19950096461 申请日期 1995.04.21
申请人 NEC CORP 发明人 KONDOU ICHIYOSHI
分类号 G11C17/00;G11C16/06;G11C16/10 主分类号 G11C17/00
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