发明名称 Mechanism for dynamically determining and distributing computer system clocks
摘要 A computer includes a mother board having a clock A thereon that provides a primary clock to a clock distribution buffer that distributes the clock that drives it to clock electronic components on the mother board. The mother board has a socket for receiving an optional module having a clock B thereon. A clock switching circuit is connected to the clock A and to the clock B socket terminus. An edge detector connected to clock B detects an edge of the clock B. A detection window indicator is asserted upon a predetermined condition, such as that power is on and stable. A control circuit, connected to the clock switching circuit, to the edge detector and to the detection window indicator causes the secondary clock to be selected and substituted for the primary clock.
申请公布号 US5572718(A) 申请公布日期 1996.11.05
申请号 US19940259472 申请日期 1994.06.14
申请人 INTEL CORPORATION 发明人 SCRIBER, MIKE;YOUNG, BRUCE
分类号 G06F1/10;(IPC1-7):G06F1/04 主分类号 G06F1/10
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