| 摘要 |
<p>PURPOSE: To obtain a high error correction rate from a digital circuit by provid ing a timing position detecting means that detects a position of a timing signal. CONSTITUTION: This device reproduces digital data demodulated from an analog signal in accordance with (d, k) rule. A comparator circuit 11 receives a signal RS reproduced by a reproducing system 10 and compares the signal RS with a specified threshold value TH and outputs a digital signal P with a shorter pulse width when the RS signal level is equal to the threshold value. Base on the signal P, VPLL 12 outputs a signal CLK of which a period corresponds to one bit of the digital signal to synchronizing circuits 141-143 as a synchronizing clock. A timing position detecting means consists of three pairs of delay circuits 131 133 and synchronizing circuits 141-143 and detects the timing position in a period of the digital data. An error judging part 152 detects that the data D1-D3 stored in the storage part 151 do not satisfy (d, k) rule and the error correcting part 153, in the case that the data include any error, outputs a control signal for correcting the data error to the storage 151.</p> |
