Bit line conditioning circuit for random access memory

摘要

A bit line conditioning circuit for a random access memory (RAM) is provided. A pair of driver transistors maintain the bit line and bit line inverse at a high voltage before a memory cell is accessed. When a memory cell is accessed, the driver transistors are turned off such that the memory cell is accessed when the bit line and bit line inverse are not statically loaded. Since the bit line and bit line inverse are not statically loaded when the access is initiated, a read or write operation occurs more quickly than in a prior art RAM. An equalization transistor is coupled across the bit line and bit line inverse, and is turned on when a memory access is initiated to equalize the value over the bit line and bit line inverse.