发明名称 PLL CIRCUIT AND PLL SYSTEM
摘要 PURPOSE: To shorten the time required for locking the frequency and phase of a system clock on a reception side and to accurately control the frequency of the system clock. CONSTITUTION: Immediately after switching a program or immediately after switching a time base or immediately after turning on a power source, after the value of PCR (time information and phase information inserted to a bit stream) is loaded to a counter 19 once, a difference between the value of the PCR and the output value of the counter 19 is obtained and the difference between the value of the PCR and the output value of the counter 19 is obtained at a timing when the PCR is sent next. Thereafter, the value of the PCR is loaded to the counter 19 and thus, the time required for locking the frequency and phase of the system clock on the reception side is shortened.
申请公布号 JPH08288880(A) 申请公布日期 1996.11.01
申请号 JP19950114016 申请日期 1995.04.14
申请人 TOSHIBA CORP 发明人 KOSHIRO NATSUKI;HIROTA ATSUSHI;SAKAMOTO NORIYA
分类号 H04N5/06;H03L7/06;H03L7/08;H03L7/093;H03L7/18;H04B1/26;H04L7/033;H04L27/22;H04N7/56 主分类号 H04N5/06
代理机构 代理人
主权项
地址