| 摘要 |
PURPOSE: To attain high speed synchronization and to obtain an excellent demodulation characteristic even when variance in delay of a received wave is high by selecting the extract method of a symbol clock and a time constant of a loop filter for a PLL depending on the reception state. CONSTITUTION: Timing extract circuits 62, 63 detect a symbol timing of a received phase modulation signal respectively by a zero crossing and a tri-state crossing and a timing detection changeover circuit 64 selects either of them. A PLL 65 has plural loop filters whose time constant differs from each other and selects any of them and generates a symbol clock synchronously with the selected timing. A controller 10 discriminates a reception state based on a reception level of a received wave and a decoding data error rate and controls the timing detection changeover circuit 64 and the PLL 65 so that the timing detection circuit 62 and the loop filter with a higher time constant are selected when large dispersion in delay of, e.g. the received wave is discriminated. |
