| 摘要 |
PURPOSE: To provide a pulse generation circuit which can secure the stable output pulse width without suffering any influence of the glitch of an input signal. CONSTITUTION: The signals S141 and S142 of phases opposite to each other are used as the reset signals for an HL edge detection circuit 11A, and an inverted signal RIN and the signal S142 having phases opposite to each other are used as the reset signals for an LH edge detection circuit 12A respectively. Then one of reset signals of both circuits 11A and 12A is produced at a front stage of a critical path. In other words, the signal S141 is produced earlier than the critical path signal S142 for the circuit 11A. On the other hand, the signal S142 is produced earlier than the critical path signal RIN for the circuit 12A. Therefore, the reset start timing is quickened. As a result, the detection circuit that is not under a detecting operation can be surely kept in a reset state even when an input signal IN has a glitch. |
