| 摘要 |
PURPOSE: To greatly speed up the circuit simulation by performing parallel processing by using a switch level model. CONSTITUTION: A logic circuit is converted into the switch level model through a physical circuit (S11) and based on the switch level model, roles are allocated to respective basic function cells (S12). Mutual combination patterns of the basic function cells are switched (S13) and the respective basic function cells makes calculations in parallel (S14). It is decided whether the calculations end (S15), and when not, the control is returned to S13. When the calculations end, delay is calculated (S16) and the processing is completed. |
