Semiconductor DRAM circuit with test mode for personal computer and workstation

摘要

The DRAM circuit includes a condition determination circuit (1610) and a test mode signal setting production circuit (1620). The determination circuit receives an input signal (A1,A2), with at least one bit, to output a state determination signal (TDA-TDC,TGA,TGB) having at least one bit in compliance to the input signal bit. The test mode production circuit receives one of these state determination signals to produce respective test mode signals (TE,TEST1-TEST7). If the input signal to the determination circuit is at one level, the test mode production circuit outputs one test mode signal (TE) to set multiple requests. The remaining test mode signals (TEST1-TEST7) are output in response if this input signal level is at a second level and if other signals (RA1-RA6) input to the production module are at an active level. Both test mode signal sets are set at an active level when the initial and secondary input signals are in respecive second and third states.