| 摘要 |
<p>A semiconductor storage device is provided with an address input circuit to which a row address signal is inputted synchronously with a row address strobe signal and a column address signal is inputted synchronously with a column address strobe signal, a memory array in which a plurality of dynamic memory cells are arranged in a matrix and address selection is performed in units of bits based on the address signal inputted through the address input circuit, a modulation circuit which pulse-modulates the data read out in the units of a plurality of bits by using the column address strobe signal as a reference signal, or a clock signal as the reference clock in the case of a synchronous dynamic RAM, and a demodulation circuit which demodulates the inputted pulse-modulated write signals. Therefore, the access speed to a memory can be substantially increased by inputting/outputting a large amount of data through pulse modulation while the input/ouput interface of an existing dynamic RAM or synchronous dynamic RAM is used as it is.</p> |
